(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of ensuring improved new tool selection, of reducing the number of iterative learning cycles required for the installation of new processing tools and of accelerating start-up of new processing tools.
(2) Description of the Prior Art
The creation of semiconductor devices typically requires numerous steps processing that have to meet the most stringent requirements of performance, cost objectives, high technical capabilities and the like. The capital that is invested to create a modern semiconductor manufacturing foundry is considerable and must therefore be balanced against large volume of production in order to make the incurred manufacturing cost per device acceptable. In addition, the art of creating semiconductor devices is a very dynamic undertaking that requires constant modifications to the existing facilities and processing tools so that competitive pressures can be met and a market position can be maintained. Therefore, not only is the initial investment a significant burden to the cost of creating semiconductor devices but this burden is constantly extended over time to be carried by present and future technologies.
Many adaptations to new processing requirements can be addressed and solved by modifying existing tools or by changing conditions of processing or materials that are applied for the process. In many applications however this approach of updating the existing is not adequate to adequately address future requirements in which case new processing tools must be provided. New processing tools offer a new set of challenges, which in most cases result in additional cost incurred by the product, a cost that is further aggravated by new procedures that must be implemented, a learning curve that must be passed in order to gain operational familiarity with the new tool, possible new materials that must be acquired and integrated into the new processing procedures, and the like. All of these aspects are inherently time-consuming and therefore inherently expensive. Many of the new tools may further require housing such tools in facilities that must meet new and upgraded requirements of clean room environment or absence of vibration or other environmental impacts on the new tools. It is not uncommon that a new building is created just to house delicate and vibration sensitive tool such as X-ray equipment or E-beam devices.
The above highlighted impact that is caused by keeping a semiconductor manufacturing facility up to date and competitive is by no means an exhaustive listing of considerations that affect such an effort of updating the processing tools and facilities. It is clear however from even such a short listing that the cost incurred in any modification of a semiconductor manufacturing environment can be significant and must therefore be a major consideration before such an action is taken.
It is therefore highly beneficial if, instead of performing an update to the manufacturing facilities by installing tools and incurring the therewith-associated cost, another method is found to simulate the operational and interactive impact of such an update.
In view of the processing capabilities of even a modestly complex computer or software program, it can be considered a natural extension of a computer program to design and use a computer program that is instrumental in addressing problems associated with acquiring, installing etc. of new, modified processing tools or even of reinstalling previously used processing tools.
Another approach is provided by sub-dividing a complete processing cycle into modules, so that each individual and identifiable unit, which comprises a sub-section of a complete or partially complete processing arrangement, can be analyzed. The invention addresses such an approach.
U.S. Pat. No. 6,263,255 (Tan et al.) shows a process control system for tools using feed forward and feed back
U.S. Pat. No. 5,761,064 (La et al.) shows a defect management system to improve semiconductor yields.
U.S. Pat. No. 6,256,549 Bl (Romero et al.) shows an integrated manufacturing solution.
A principle objective of the invention is to provide a method that ensures improved tool selection for modification or updating of a semiconductor manufacturing foundry.
Another objective of the invention is to reduce the number of iterative learning cycles that are typically required for modification or updating of a semiconductor manufacturing foundry.
Yet another objective of the invention is to provide a method that allows accelerated process and fabrication start-up after modification or updating of a semiconductor manufacturing foundry.
In accordance with the objectives of the invention a new methodology is provided that assures that integrated process results are verified and assured prior to the installation of processing tools as part of modifying or updating of a semiconductor manufacturing foundry. The complete semiconductor manufacturing complement of processing tools is sub-divided into short-loops or sub-modules, which are then combined into a full loop. This combination of sub-modules into modules that closer approach a full complement of processing tools can be accomplished in a gradual manner, whereby one or more sub-loops are first combined and evaluated, to this combination one or more additional sub-groups may be added whereby each of these latter sub-groups may also have been created by combining one or more (original) sub-loops. This process is continued to the point where a full complement of process equipment has been created, completing the full processing loops of the semiconductor manufacturing facility.